1 radiation hardened high speed dual voltage comparators isl7119rh, ISL7119EH the isl7119rh, ISL7119EH are radiation hardened, high speed, dual voltage comparat ors fabricated on a single monolithic chip. they are designed to operate over a wide dual supply voltage range as well as a single 5v logic supply and ground. the open collector output stage facilitates interfacing with a variety of logic devices an d has the ability to drive relays and lamps at output currents up to 25ma. the isl7119rh, ISL7119EH are fabr icated on our dielectrically isolated rad-hard silicon gate (rsg) process, which provides immunity to single event latch-up (sel) and highly reliable performance in the natural space environment. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed below must be used when ordering. detailed electrical specifications for the isl7119rh, ISL7119EH are contained in smd 5962-07215. a ?hot-link? is provided on our website for downloading. pin configuration s isl7119rh, ISL7119EH (10 ld flatpack gdfp1-f10 or cdfp2-f10) top view features ? electrically screened to dla smd # 5962-07215 ? qml qualified per mil-prf-38535 requirements ? radiation environment - total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 x 10 5 rad(si) - sel/seb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . immune ? input offset voltage (v io ) . . . . . . . . . . . . . . . . . . . . 8mv (max) ? input bias current (i bias ) . . . . . . . . . . . . . . . . . 1000na (max) ? input offset current (i io ) . . . . . . . . . . . . . . . . . . . .150na (max) ? saturation voltage @ i sink = 3.2ma (v sat ) . . . . 0.65v (max) ? saturation voltage @ i sink = 25ma (v sat ) . . . . . . 1.8v (max) ? response time (t pd ) . . . . . . . . . . . . . . . . . . . . . . . 160ns (max) applications ?window detector ? level shifter ?relay driver ?lamp driver 10 9 8 7 6 2 3 4 5 1 out 1 gnd 1 +in 1 -in 1 -v s +v s -in 2 +in 2 gnd 2 out 2 ordering information ordering number internal mkt. number part marking temp. range (c) package (pb-free) pkg. dwg. # 5962f0721501qxc isl7119rhqf (note) q 5962f07 21501qxc -55 to +125 10 lead ceramic metal seal flatpack k10.a 5962f0721501vxc isl7119rhvf (note) q 5962f07 21501vxc -55 to +125 10 lead ceramic metal seal flatpack k10.a 5962f0721502vxc ISL7119EHvf (note) q 5962f07 21502vxc -55 to +125 10 lead ceramic metal seal flatpack k10.a 5962f0721501v9a isl7119rhvx -55 to +125 10 lead ceramic metal seal flatpack k10.a 5962f0721502v9a ISL7119EHvx -55 to +125 10 lead ceramic metal seal flatpack k10.a isl7119rhf/proto isl7119rhf/proto (note) isl7 119rhf /proto -55 to +125 10 lead ceramic metal seal flatpack k10.a isl7119rhx/sample isl7119rhx/sample die note: these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2007, 2008, 2011, 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. april 5, 2012 fn6607.4
isl7119rh, ISL7119EH 2 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6607.4 april 5, 2012 for additional products, see www.intersil.com/product_tree die characteristics die dimensions: 2030m x 2030m (~80 mils x 80 mils) thickness: 483m 25.4m (19 mils 1 mil) interface materials: glassivation: type: psg (phosphorous silicon glass) thickness: 8.0k? 1.0k? top metallization: type: alsicu thickness: 16.0k? 2k? substrate: radiation hardened silicon gate, dielectric isolation backside finish: silicon assembly related information: substrate potential: unbiased (di) additional information: worst case current density: <2.0 x 10 5 a/cm 2 transistor count: 66 metallization mask layout isl7119rh, ISL7119EH
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